Described below is a method and apparatus for manufacturing an electronic module which has a substrate on which at least one component, in particular a semiconductor chip, is arranged.
The starting point for manufacturing the electronic module is the semifinished electronic module shown schematically in cross-section in FIG. 1 and marked with the reference character 10. A structured metal layer 12 with metal or contact areas 13, 14, 15 is applied to a substrate 11. A component 16, 19, e.g. a semiconductor chip, is mounted on the contact areas 13, 14 respectively. The component 16 is connected to the contact area 13 by way of a connection 22, generally a solder. The component 19 is connected correspondingly to the contact area 14 by way of a connection 23. If the components have a backside contact, in other words a contact facing the substrate 11, the connection 22, 23 establishes both a mechanical and an electrical connection to the respective contact area 13 and/or 14. For electrical contacting purposes the components 16, 19 each have a number of contact areas on their top side facing away from the substrate 11. For example the components 16, 19 each include two contact areas 17, 18 or 20, 21. The electrical connection between the contact areas 17, 18 or 20, 21 and the (just by way of example) one contact area 15 is generally achieved using bonding wires (not shown).
Alternatively electrical connections can be established between the contact areas 17, 18 or 20, 21 of the components 16, 19 and the contact area 15 using what is termed planar interconnection technology, in which a surface 29 of the semifinished product is first covered with an insulating layer. Openings are made in the insulating film at the sites of the contact areas 15, 17, 18, 20, 21 to expose the contact areas. A sputter layer is then applied to the insulating film and its openings to provide full coverage. The sputter layer generally has an approximately 50 nm thick titanium layer and an approximately 1 μm thick copper layer. A further light-sensitive film (called photo-film), generally made of an insulating material, is applied to, this sputter layer. The photo-film is generally between 100 and 200 μm thick and in a later step is exposed and developed according to the desired conducting structure.
Exposure generally takes place using a mask which is used to transfer the layout of the conducting structure onto the photo-film. The mask shades those sections of the photo-film that are to form the subsequent electrically conducting structure. The unexposed sections of the photo-film can be removed in a further operation to expose the underlying sputter layer, or more precisely the copper surface. Immersing the prepared semifinished product in an electrolyte bath, in particular a copper electrolyte bath, causes an approximately 100 to 200 μm thick copper layer to be grown due to galvanic reinforcement. In a subsequent step, referred to as stripping the photo-film, the photo-film still present on the surface in regions where no electrically conducting structure is to be formed is removed. The last step involves what is termed differential etching, in which the entire sputter layer of titanium and copper is removed so that only the desired conductive structure remains.
The application of the insulating film to the surface 29 of the semifinished product 10 is critically important for the reliability of an electronic module manufactured in this manner. The quality of adhesion and any air inclusions between the insulating film and the surface 29 can influence the electrical characteristics or even lead to the destruction of the electronic module during operation. This is so particularly when the components 16, 19 are power semiconductor components which are embodied to switch voltages in the range from 400 V to 10 kV. As well as influencing the insulation characteristics of the insulating film (generally in the range from 60 to 100 kV/mm for an insulating film with a thickness of 100 to 400 μm) the presence of any air inclusions in particular influences the electric field strength range and therefore the characteristics of the subsequent electronic module. Critical points here are in particular the upper lateral-edge shown with the reference character 24 in FIG. 1 and the lower lateral edge of the component 19 shown with the reference character 25. These problems affect all the corresponding lateral edges of this and other components, even though this is not shown specifically with reference characters in the figure.